ASIC-Lab
The ASIC laboratory at the FTD supports detector developments for particle physics experiments and for imaging applications. Our main focus is on pixel detectors - implemented as hybrid (separate sensor and signal processing layers) or monolithic (charge sensing and signal processing in the same CMOS layer) designs. The technologies used for the chip developments include TSMC 65 nm, TSMC 28 nm, TJ 180 nm, LF 150 nm and others.
Monolithic Pixel Detectors
- R&D for pixel detector upgrades at the LHC (MONOPIX series of chips)
- Upgrade of the Belle 2 vertex detector (OBELIX)
- Upgrade of the LHC-B pixel tracker (MIGHTYPIX)
Hybrid Pixel Detectors
- Pixel detector readout chip for the HL-LHC upgrade of ATLAS and CMS experiments (RD53 series of chips)
- X-ray imaging detector for the European X-FEL beamline at DESY (CORDIA, AGIPD chips)
R&D directions
- Radiation hard embedded FPGA (eFPGA) in advanced CMOS technologies
- Radiation hard embedded microcontrollers (RISC-V)
Other Detectors
- Digital r/o chip for DEPFET pixel sensor based pixel vertex detector (PXD) at the Belle 2 experiment (DHPT chip)
- Electron Imaging with DEPFET pixel detectors, EDET (DMC chip)
Kontakt
Hans Krüger
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